Resource Sharing in ALU Multiplexing

High-speed datapaths in processors often contain multiple arithmetic operations selected by control signals. Writing naive conditional statements with heavy arithmetic in every branch forces the synthesis tool to instantiate redundant hardware, exploding the gate count and power consumption.

This module computes the sum of either A and B, or C and D, based on a selection signal sel. To minimize area, the design must share a single 32-bit adder. The multiplexing of the operands must occur before the addition operation. The final sum is registered on the clock edge.

Positive-edge triggered clock clk. Asynchronous active-low reset rst_n. On reset, the result register must be cleared to 0. The reset signal has priority over all other inputs. Addition overflow is ignored, and the result naturally wraps around within the 32-bit width.

Cycle 1: rst_n=0, sel=X, A=X, B=X, C=X, D=X → result updates to 0 Cycle 2: rst_n=1, sel=1, A=10, B=20, C=30, D=40 → result updates to 30 Cycle 3: rst_n=1, sel=0, A=10, B=20, C=30, D=40 → result updates to 70 Cycle 4: rst_n=1, sel=1, A=5, B=5, C=30, D=40 → result updates to 10 Cycle 5: rst_n=1, sel=0, A=5, B=5, C=100, D=100 → result updates to 200

{ "signal": [
  { "name": "clk",   "wave": "p......" },
  { "name": "rst_n", "wave": "01....." },
  { "name": "sel",   "wave": "x1010." },
  { "name": "A",     "wave": "x====.", "data": ["10", "10", "5", "5"] },
  { "name": "B",     "wave": "x====.", "data": ["20", "20", "5", "5"] },
  { "name": "C",     "wave": "x====.", "data": ["30", "30", "30", "100"] },
  { "name": "D",     "wave": "x====.", "data": ["40", "40", "40", "100"] },
  {},
  { "name": "result","wave": "x=====", "data": ["0", "30", "70", "10", "200"] }
], "head": { "text": "Result updates on the clock edge following the input stimulus." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears result to 0 when asserted | | sel | input | 1 | Selects operands: 1 for A+B, 0 for C+D | | A | input | 32 | First operand for selection 1 | | B | input | 32 | Second operand for selection 1 | | C | input | 32 | First operand for selection 0 | | D | input | 32 | Second operand for selection 0 | | result | output | 32 | Registered sum of the selected operands |

Constraints

• The clock edge is posedge, and the reset is negedge asynchronous.
• The result output must be registered.
• The design must instantiate exactly one 32-bit adder. Do not write A + B and C + D in separate conditional branches.
• Any addition overflow must wrap around normally within the 32-bit width.

Topics

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