Sequential For Loop Shift Register

HardVerilog / SystemVerilogBuild

Digital signal processing pipelines and delay lines frequently require parameterized shift registers to align data streams across multiple clock cycles. The module acts as a configurable delay line. When enabled, it captures the input data and shifts existing data down a chain of registers. The output exposes the final register in the chain, effectively delaying the input by a parameterized number of clock cycles.

Clock edge: posedge clk
Reset type: Asynchronous active-low
Reset polarity: When rst_n is 0, all internal shift register stages and d_out clear to 0.
Priority rules: Reset takes priority over all other operations. When rst_n is 1, the en signal dictates operation.
Operation: On the clock edge, if en is 1, d_in is loaded into the first stage, and stage i moves to stage i+1. If en is 0, all stages hold their current values.
Output: The output d_out is continuously driven by the final stage of the shift register (DEPTH-1).

Worked Trace (DEPTH=4, WIDTH=8): Cycle 1: rst_n=0 → stages=[00, 00, 00, 00], d_out=00 Cycle 2: rst_n=1, en=1, d_in=AA → stages=[AA, 00, 00, 00], d_out=00 Cycle 3: en=1, d_in=BB → stages=[BB, AA, 00, 00], d_out=00 Cycle 4: en=1, d_in=CC → stages=[CC, BB, AA, 00], d_out=00 Cycle 5: en=1, d_in=DD → stages=[DD, CC, BB, AA], d_out=AA Cycle 6: en=0, d_in=EE → stages=[DD, CC, BB, AA], d_out=AA (hold)

{ "signal": [
  { "name": "clk",   "wave": "p......" },
  { "name": "rst_n", "wave": "01....." },
  { "name": "en",    "wave": "01...0." },
  { "name": "d_in",  "wave": "x======", "data": ["AA", "BB", "CC", "DD", "EE"] },
  {},
  { "name": "d_out", "wave": "=======", "data": ["00", "00", "00", "00", "00", "AA", "AA"] }
], "head": { "text": "Cycle-by-cycle shift operation with DEPTH=4." } }

| Parameter | Default | Description | |-----------|---------|-------------| | DEPTH | 8 | Number of stages in the shift register | | WIDTH | 8 | Bit width of the data path |

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset | | en | input | 1 | Active-high shift enable | | d_in | input | WIDTH | Data input to the first stage | | d_out| output | WIDTH | Data output from the final stage |

Constraints

The module must be parameterized with DEPTH and WIDTH using exactly those parameter names.
You must use a for loop inside a clocked procedural block to define the shift register stages.
Output values must transition exactly on the clock edge, reflecting the updated internal state.
All internal register stages must be explicitly cleared to 0 upon reset.

Topics

SequentialParameterizedShift RegisterFor Loop

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