Serial In Serial Out with Valid Flag
Data streams moving across chip boundaries or through deep processing pipelines often require synchronization of the data itself with a signal indicating its validity. A pure shift register delays data, but downstream logic must know exactly which output bits represent real data versus undefined startup zeroes or gaps in transmission.
The module acts as an 8-stage serial-in, serial-out (SISO) shift register with an accompanying valid flag pipeline. Serial data arrives on d_in alongside a valid signal on v_in. Both the data and the valid flag must be delayed by exactly 8 clock cycles. The output d_out presents the delayed data, while v_out asserts high only when the data currently on d_out originated from a cycle where v_in was asserted.
Timing and reset rules: • Clock edge: posedge clk • Reset type: Asynchronous, active-low (rst_n) • Output values on reset: Both d_out and v_out must clear to 0 • Internal state on reset: All 8 internal pipeline stages for both data and valid tracking must clear to 0
Worked trace: Cycle 1: rst_n=0 → d_out=0, v_out=0 (Pipeline cleared) Cycle 2: rst_n=1, d_in=1, v_in=1 → d_out=0, v_out=0 (Data enters stage 1) Cycle 3: rst_n=1, d_in=0, v_in=1 → d_out=0, v_out=0 (Data enters stage 2) Cycle 4: rst_n=1, d_in=1, v_in=0 → d_out=0, v_out=0 (Data enters stage 3) Cycle 5: rst_n=1, d_in=0, v_in=0 → d_out=0, v_out=0 (Data enters stage 4) Cycle 6: rst_n=1, d_in=1, v_in=1 → d_out=0, v_out=0 (Data enters stage 5) Cycle 7: rst_n=1, d_in=1, v_in=1 → d_out=0, v_out=0 (Data enters stage 6) Cycle 8: rst_n=1, d_in=0, v_in=0 → d_out=0, v_out=0 (Data enters stage 7) Cycle 9: rst_n=1, d_in=0, v_in=0 → d_out=1, v_out=1 (Cycle 2 data emerges from stage 8) Cycle 10: rst_n=1, d_in=0, v_in=0 → d_out=0, v_out=1 (Cycle 3 data emerges from stage 8)
{ "signal": [
{ "name": "clk", "wave": "p........." },
{ "name": "rst_n", "wave": "01........" },
{ "name": "d_in", "wave": "0101011000" },
{ "name": "v_in", "wave": "0110011000" },
{},
{ "name": "d_out", "wave": "0.......10" },
{ "name": "v_out", "wave": "0.......11" }
], "head": { "text": "Data and valid flag emerge exactly 8 cycles after insertion." } }| Signal | Direction | Width | Description | |---|---|---|---| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears all pipeline stages to 0 | | d_in | input | 1 | Serial data input | | v_in | input | 1 | Valid flag input corresponding to d_in | | d_out | output | 1 | Serial data output, delayed by 8 clock cycles | | v_out | output | 1 | Valid flag output, delayed by 8 clock cycles |
Constraints
- The design must use exactly an 8-stage pipeline delay for both data and valid signals
- Clock is positive-edge triggered
- Reset is active-low and asynchronous
- Outputs
d_outandv_outmust be registered (they are the outputs of the 8th flip-flops)
Topics
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