Shift Register Inference

High-speed digital pipelines often require data to be delayed by a fixed number of clock cycles to align with parallel processing paths. When these delay chains are coded carefully without resets, synthesis tools (like Yosys or Vivado) can pack them into highly efficient Shift Register Lookup Tables (SRLs) rather than consuming individual flip-flops.

The module acts as a 16-stage, 8-bit wide delay line. On every positive clock edge, the input data enters the first stage of the shift register, and the existing data shifts down the chain. The output presents the data that was sampled exactly 16 clock cycles ago. To ensure the synthesis tool infers an SRL, this module deliberately omits a reset signal.

Timing and Reset Rules

• Clock edge: posedge clk
• Reset: None. The circuit must not contain any synchronous or asynchronous reset logic.
• Initial State: Uninitialized. For simulation purposes, the testbench will flush the pipeline with zeros before evaluating the output.
• Output: The output dout is registered and must reflect the value of din from exactly 16 clock cycles prior.

Worked Trace

• Cycle 1: din = 8'hAA, clk posedge → internal stage 1 stores 8'hAA, dout is unknown.
• Cycle 2: din = 8'hBB, clk posedge → internal stage 1 stores 8'hBB, internal stage 2 stores 8'hAA, dout is unknown.
• Cycle 16: din = 8'hCC, clk posedge → dout outputs 8'hAA (the value sampled on Cycle 1).
• Cycle 17: din = 8'hDD, clk posedge → dout outputs 8'hBB (the value sampled on Cycle 2).

Timing Diagram

{ "signal": [
  { "name": "clk",  "wave": "p................." },
  { "name": "din",  "wave": "x=................", "data": ["D0"] },
  { "name": "dout", "wave": "x................=", "data": ["D0"] }
],
"head": { "text": "Data appears on dout exactly 16 clock cycles after being sampled on din." }
}

Port Table

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | din | input | 8 | Data input to be delayed | | dout | output | 8 | Data output, delayed by exactly 16 clock cycles |

Constraints

• The module must strictly delay din by 16 clock cycles on posedge clk.
• Do not include any reset logic; adding a reset will prevent SRL inference in many FPGA architectures.
• The output dout must be driven by the 16th register stage.
• The data path is 8 bits wide.

Topics

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