Shift Register Pattern Debounce

Mechanical switches and fast asynchronous signals often exhibit bounce, causing multiple false logic transitions before settling. A shift-register-based debouncer provides a low-latency, resource-efficient alternative to counter-based debouncers by continuously sampling the input into a sliding window.

The module maintains an 8-bit history of the input signal. On every clock cycle, the newest input bit is shifted into the register. The output updates based on a strict hysteresis rule: it transitions to 1 only when all 8 bits of the history are 1, and transitions to 0 only when all 8 bits are 0. If the history contains a mix of 1s and 0s, the output holds its previous value. This ensures that brief glitches or bounces are entirely ignored once the signal has stabilized.

The shift register updates on the positive edge of the clock. To minimize latency, the output clean_out must update on the exact same clock edge that the shift register achieves an all-ones or all-zeros state.

Worked Trace: Cycle 1: rst_n=0 → shift_reg=8'h00, clean_out=0 Cycle 2: rst_n=1, noisy_in=1 → shift_reg=8'h01, clean_out=0 Cycle 3: noisy_in=1 → shift_reg=8'h03, clean_out=0 Cycle 8: noisy_in=1 → shift_reg=8'h3F, clean_out=0 Cycle 9: noisy_in=1 → shift_reg=8'h7F, clean_out=0 Cycle 10: noisy_in=1 → shift_reg=8'hFF, clean_out=1 (Asserts) Cycle 11: noisy_in=0 → shift_reg=8'hFE, clean_out=1 (Holds state)

{ "signal": [
  { "name": "clk",       "wave": "p........." },
  { "name": "rst_n",     "wave": "01........" },
  { "name": "noisy_in",  "wave": "01.......0" },
  {},
  { "name": "shift_reg", "wave": "==========", "data": ["00", "01", "03", "07", "0F", "1F", "3F", "7F", "FF", "FE"] },
  { "name": "clean_out", "wave": "0.......1." }
], "head": { "text": "clean_out asserts on the same clock edge the shift register becomes 8'hFF" } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all state and outputs go to 0 when asserted | | noisy_in | input | 1 | Raw input signal to be debounced | | clean_out | output | 1 | Debounced output with hysteresis; registered |

Constraints

• The internal shift register must be 8 bits wide.
• The shift register must shift left, meaning noisy_in is shifted into the least significant bit (LSB).
• clean_out must be a registered output, not purely combinational logic.
• clean_out must assert on the exact same posedge clk that the shift register's next state becomes 8'hFF.
• Both the internal shift register and clean_out must be reset to 0 asynchronously when rst_n is 0.

Topics

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