Signed Arithmetic and Sign Extension
Digital signal processing datapaths frequently require signed arithmetic. Verilog's default evaluation rules aggressively coerce mixed or unannotated vectors into unsigned types. A single unsigned wire in an expression can silently destroy the arithmetic integrity of the entire pipeline by preventing automatic sign extension.
The module computes the product of two 8-bit two's complement signed integers. The result is a 16-bit two's complement signed integer. Both inputs arrive as standard logic vectors and must be correctly interpreted as signed values before multiplication to ensure the sign bit is preserved and extended into the upper byte of the result.
This circuit is purely combinational. There is no clock and no reset. The output must reflect the valid signed product of the inputs at all times.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 8 | Multiplicand; represents a signed two's complement integer | | b | input | 8 | Multiplier; represents a signed two's complement integer | | p | output | 16 | Product; represents a signed two's complement integer |
Constraints
- The circuit must be purely combinational.
- Inputs
aandbare provided as standard unannotated vectors but must be treated as signed two's complement values. - Output
pmust be a valid 16-bit signed two's complement representation of the product. - Do not use any clock or reset signals.
Topics
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