Variable Indexed Part Select
Packet parsers and memory controllers frequently need to extract specific bytes from wide data buses based on dynamic offsets. When processing a 64-bit word, a common requirement is to multiplex out a single 8-bit chunk without writing an exhaustive case statement.
This module acts as a dynamic byte extractor. It receives a 64-bit data word and a 3-bit index. The index dictates which 8-bit segment of the input word is routed to the output. An index of 0 selects the least significant byte (bits 7 down to 0). An index of 7 selects the most significant byte (bits 63 down to 56). The extraction must be implemented using Verilog's indexed part-select operator to infer the multiplexing logic efficiently.
This is a purely combinational circuit. There are no clocks, resets, or sequential elements. The output must update immediately when either the data or the index changes.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | data_in | input | 64 | The full 64-bit input data word | | byte_idx | input | 3 | The 0-indexed byte position to extract | | byte_out | output | 8 | The extracted 8-bit data |
Constraints
- The circuit must be purely combinational.
- The
byte_idxinput ranges from 0 to 7. - The output must reflect the exact 8-bit segment corresponding to the index.
Topics
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