Static Cast Integer to Enum
Packet parsers receive raw bit streams from physical interfaces that must be interpreted as strongly typed enumerations for downstream processing. Directly assigning raw bits to an enumerated type in SystemVerilog is illegal and causes compilation failures. A static cast must be used, but casting an undefined integer value into an enum creates undefined behaviour in hardware.
The packet_type_parser module receives a 4-bit raw_type along with a valid_in signal. On every clock cycle where valid_in is asserted, the module verifies if raw_type corresponds to a defined packet type. If the type is known, it asserts valid_out and outputs the statically cast enumeration value on parsed_type. If the type is unknown, it asserts type_err, deasserts valid_out, and holds the previous valid parsed_type value. When valid_in is low, both valid_out and type_err are deasserted, and parsed_type holds its value.
Timing and Reset Rules: • Clock edge: posedge clk • Reset type: Asynchronous • Reset polarity: Active-low (rst_n) • Output values on reset: valid_out goes to 0, type_err goes to 0, and parsed_type goes to PKT_DATA. • Priority rules: Reset overrides all other inputs. All outputs are registered and update strictly on the clock edge.
Worked Trace: Cycle 1: rst_n=0 → Outputs reset to valid_out=0, type_err=0, parsed_type=PKT_DATA. Cycle 2: rst_n=1, valid_in=1, raw_type=4'd2 (PKT_ACK) → Clock edge occurs. Cycle 3: Outputs update to valid_out=1, type_err=0, parsed_type=PKT_ACK. Inputs are valid_in=1, raw_type=4'd9 (Invalid) → Clock edge occurs. Cycle 4: Outputs update to valid_out=0, type_err=1, parsed_type=PKT_ACK (held). Inputs are valid_in=0, raw_type=4'dx → Clock edge occurs. Cycle 5: Outputs update to valid_out=0, type_err=0, parsed_type=PKT_ACK (held). Inputs are valid_in=1, raw_type=4'd4 (PKT_PING) → Clock edge occurs. Cycle 6: Outputs update to valid_out=1, type_err=0, parsed_type=PKT_PING.
{ "signal": [
{ "name": "clk", "wave": "p......" },
{ "name": "rst_n", "wave": "01....." },
{ "name": "valid_in", "wave": "x1101.." },
{ "name": "raw_type", "wave": "x==x=..", "data": ["2", "9", "4"] },
{},
{ "name": "valid_out", "wave": "0.10.1." },
{ "name": "type_err", "wave": "0..10.." },
{ "name": "parsed_type", "wave": "=.=..=.", "data": ["DATA", "ACK", "PING"] }
], "head": { "text": "Cycle-by-cycle type parsing and error handling." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset | | valid_in | input | 1 | Indicates raw_type contains a new packet type to parse | | raw_type | input | 4 | Raw integer representing the packet type | | valid_out | output | 1 | Asserted for one cycle if a valid type was successfully parsed | | parsed_type| output | 4 | Strongly typed enum output (pkt_type_e); holds previous value on error or idle | | type_err | output | 1 | Asserted for one cycle if valid_in is high but raw_type is undefined |
Constraints
- The module must correctly filter out any 4-bit integer that is not explicitly defined in the
pkt_type_eenumeration. - SystemVerilog strictly forbids direct assignment of a logic vector to an enum type variable; you must cast it.
parsed_typemust not update if the incomingraw_typeis invalid.
Topics
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