Strongly Typed Enum State Machine

Hardware debug time is heavily influenced by waveform readability. When a state machine uses standard parameters, waveform viewers display raw integer values, forcing engineers to manually decode states. SystemVerilog strongly typed enums solve this by embedding state names directly into the simulation database and allowing the compiler to catch invalid state assignments.

A two-agent fixed-priority arbiter manages access to a shared resource. The arbiter waits in an IDLE state. When requests arrive, it grants access to agent 0 over agent 1. Once an agent is granted, it holds the grant until it drops its request, at which point the arbiter returns to IDLE before granting the next request.

Clocking is on posedge clk. The module uses an asynchronous active-low reset rst_n. On reset, all outputs and the internal state are driven to 0. If both requests are asserted while the arbiter is in IDLE, req0 has strict priority. Outputs gnt0 and gnt1 are combinational Moore outputs determined strictly by the current state. The state_out port continuously outputs the current 2-bit state value.

Cycle 1: rst_n=0 → state=IDLE, gnt0=0, gnt1=0, state_out=0 Cycle 2: rst_n=1, req0=0, req1=0 → state=IDLE, gnt0=0, gnt1=0, state_out=0 Cycle 3: req0=1, req1=0 → state=GRANT0, gnt0=1, gnt1=0, state_out=1 Cycle 4: req0=1, req1=1 → state=GRANT0, gnt0=1, gnt1=0, state_out=1 (hold) Cycle 5: req0=0, req1=1 → state=IDLE, gnt0=0, gnt1=0, state_out=0 (release) Cycle 6: req0=0, req1=1 → state=GRANT1, gnt0=0, gnt1=1, state_out=2

flowchart LR
    RESET(( )) -->|reset| IDLE
    IDLE((IDLE)) -->|req0=1| GRANT0
    IDLE -->|req0=0, req1=1| GRANT1
    IDLE -->|req0=0, req1=0| IDLE
    GRANT0(["GRANT0 ★"]):::out -->|req0=1| GRANT0
    GRANT0 -->|req0=0| IDLE
    GRANT1(["GRANT1 ★"]):::out -->|req1=1| GRANT1
    GRANT1 -->|req1=0| IDLE
    classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all outputs go to 0 when asserted | | req0 | input | 1 | Request from agent 0 (highest priority) | | req1 | input | 1 | Request from agent 1 | | gnt0 | output | 1 | Grant for agent 0; asserted when state is GRANT0 | | gnt1 | output | 1 | Grant for agent 1; asserted when state is GRANT1 | | state_out | output | 2 | Current FSM state; matches enum integer value |

Constraints

• Clock edge is posedge clk and reset is asynchronous active-low.
• All outputs reset to 0.
• req0 has priority over req1 when multiple requests are asserted in the IDLE state.
• The FSM must use the provided arb_state_t enum type for its internal state variables.
• Assigning an integer directly to the state variable (e.g., state = 2'b01;) will cause a deliberate SystemVerilog type error. You must use the enum labels (e.g., GRANT0).
• Outputs gnt0 and gnt1 must be purely combinational.
• The arbiter is non-preemptive. A granted agent cannot be interrupted by a higher-priority request.

Topics

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