SystemVerilog Port Connection Shorthand
Complex System-on-Chip (SoC) designs often contain top-level structural modules that do nothing but wire together dozens of sub-modules. Standard Verilog-2001 instantiation requires typing every signal name twice, leading to bloated code and copy-paste errors. SystemVerilog introduces port connection shorthands (.name and .*) to cleanly connect matching port and net names, drastically reducing visual noise and preventing implicit wire bugs.
A three-stage instruction pipeline requires structural connection. The pipeline consists of three pre-defined child modules: fetch_stage, decode_stage, and execute_stage. The top-level module routes the external control signals to these stages and connects the intermediate data paths between them.
The pipeline stages behave as follows: • fetch_stage increments an instruction word when enabled and asserts a valid signal. • decode_stage splits the instruction into an opcode and operand. • execute_stage adds the opcode and operand to produce a final result.
Because the pipeline has three stages, an instruction fetched on cycle 2 will produce a valid result on cycle 4.
Timing and Reset Rules: • Clock edge: clk is positive-edge triggered. • Reset type: rst_n is an asynchronous, active-low reset. • Output values on reset: result goes to 8'h00, valid_out goes to 1'b0. All internal pipeline stages also reset to zero.
Worked Trace: Cycle 1: rst_n=0, en=0 → Pipeline resets. result=0, valid_out=0. Cycle 2: rst_n=1, en=1 → Fetch stage receives enable. result=0, valid_out=0. Cycle 3: rst_n=1, en=1 → Decode stage processes first instruction. result=0, valid_out=0. Cycle 4: rst_n=1, en=0 → Execute stage processes first instruction. result=6, valid_out=1. Cycle 5: rst_n=1, en=0 → Execute stage processes second instruction. result=12, valid_out=1. Cycle 6: rst_n=1, en=0 → Pipeline drains. result=12, valid_out=0.
Top-Level Ports:
| Signal | Direction | Width | Description | |-------------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset | | en | input | 1 | Pipeline enable signal | | result | output | 8 | Final computed result | | valid_out | output | 1 | High when result contains valid data |
Constraints
- You must instantiate
fetch_stage,decode_stage, andexecute_stagewithin your top-level module. - You must use SystemVerilog
.nameor.*shorthand to connect the modules. - You must declare the intermediate logic wires with exact name matches to the child module ports.
- Do not modify the provided child module definitions.
Topics
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