Synchronous Reset Inference
Standard cell libraries and FPGA architectures often provide flip-flops with dedicated asynchronous reset pins. However, when a design requires a synchronous reset, the synthesis tool must route the data through a two-to-one multiplexer before it reaches the data pin of the flip-flop. This adds a combinational logic level to the data path, which can impact timing closure in high-speed designs.
The module implements an 8-bit data register with a synchronous active-high reset. When the reset is asserted during a clock edge, the register output becomes zero regardless of the data input. When the reset is de-asserted, the register captures the value of the data input on the clock edge.
Timing and reset rules: • Clock edge: posedge clk • Reset type: Synchronous • Reset polarity: Active-high rst • Output value on reset: q becomes 8'b00000000 • Priority rules: rst has priority over d
Cycle 1: rst=1, d=8'hAA → q=8'h00 (Reset) Cycle 2: rst=0, d=8'h55 → q=8'h55 (Capture data) Cycle 3: rst=0, d=8'h33 → q=8'h33 (Capture data) Cycle 4: rst=1, d=8'hFF → q=8'h00 (Synchronous reset priority) Cycle 5: rst=0, d=8'h0F → q=8'h0F (Capture data)
{ "signal": [
{ "name": "clk", "wave": "p...." },
{ "name": "rst", "wave": "10010" },
{ "name": "d", "wave": "=====", "data": ["8'hAA", "8'h55", "8'h33", "8'hFF", "8'h0F"] },
{ "name": "q", "wave": "=====", "data": ["8'h00", "8'h55", "8'h33", "8'h00", "8'h0F"] }
], "head": { "text": "Synchronous reset clears output on the clock edge." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst | input | 1 | Synchronous active-high reset; clears q to 0 when asserted | | d | input | 8 | Data input | | q | output | 8 | Registered data output; resets to 8'h00 |
Constraints
- Clock edge must be positive.
- Reset must be synchronous and active-high.
- Output
qmust be registered, not combinational. - Reset must take priority over data input.
Topics
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