SystemVerilog Always Latch vs Always Comb
Intent-based procedural blocks in SystemVerilog instruct EDA tools on the exact hardware a designer expects to synthesize.
The code provided contains a conditional assignment for signal q based on en and d, but it lacks a default assignment. Initially, the block was declared with always_comb, which caused the synthesis tool to throw an unintended latch warning. A junior engineer changed the declaration to always_latch to silence the warning.
Evaluate the synthesis behavior and timing implications of this block type change. Determine why manipulating the block declaration alters tool output but fails to resolve the underlying hardware flaw.
Constraints
- Assume standard SystemVerilog-2012 synthesis semantics.
- Assume
enanddare asynchronous inputs to the procedural block. - The target standard cell library contains standard combinational gates, latches, and flip-flops.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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