Interpreting Yosys Latch Warnings
Synthesis tools are notoriously verbose, but missing a single inferred latch warning can lead to timing failures and functional bugs in silicon.
The log snippet below is generated by Yosys during the synthesis of an instruction decoder module.
8. Executing PROC_DLATCH pass (convert processes to latches).
Warning: Latch inferred for signal `\decode.\alu_op' from process `\decode.$proc$decode.v:25$3' at decode.v:27.
Warning: Latch inferred for signal `\decode.\valid_out' from process `\decode.$proc$decode.v:25$3' at decode.v:31.Analyze the log output to determine the affected signals, the origin of the process, and the specific line numbers causing the inference.
Constraints
- Read the log syntax carefully to distinguish between signal names, process IDs, and source file locations.
- Assume standard Verilog RTL synthesis behavior.
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