The Incomplete Sensitivity List Fallback
A 2-to-1 multiplexer routes one of two data inputs to a single output based on a select signal.
Expected behavior:
| Sel | A | B | Y | |-------|-----|-----|-----| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | | 1 | 0 | 1 | 1 | | 1 | 1 | 1 | 1 |
Simulation shows Y = 0 when transitioning to input Sel=1, A=0, B=1 from a previous state of Sel=0, A=0, B=1. The output fails to update when only the select line toggles. Inspect the RTL and correct the fault.
Constraints
- Use modern SystemVerilog constructs for combinational logic.
- Do not use legacy Verilog-2001 sensitivity lists.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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