Intermediate Variables in Combinational Blocks
Memory management units often apply a sequence of transformations to a base address before distributing it to parallel memory channels. The address generation unit must calculate a shared, scrambled base address that is then simultaneously applied to multiple memory banks.
The module computes final memory addresses through a precise sequence of operations. First, it calculates an intermediate sum by adding an offset to the base address. Next, it applies a bitwise XOR scramble mask to this intermediate sum to produce a shared scrambled base. Finally, this shared scrambled base is added to two independent channel indices to compute the final output addresses for channel 0 and channel 1. All inputs and outputs are 8-bit wide. The operations must evaluate purely combinationally without clock delays.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | base_addr | input | 8 | The starting base address | | offset | input | 8 | The primary offset added to the base address | | scramble_mask | input | 8 | Bitwise XOR mask applied to the intermediate sum | | idx_0 | input | 8 | Independent channel 0 index | | idx_1 | input | 8 | Independent channel 1 index | | addr_0 | output | 8 | Final computed address for channel 0 | | addr_1 | output | 8 | Final computed address for channel 1 |
Constraints
- All outputs must be strictly combinational.
- Overflows during addition must wrap around naturally within the 8-bit width.
- Operations must occur precisely in the specified order: addition first, then XOR, then final additions.
Topics
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