The Missing Else Latch
Address decoders must explicitly define outputs for all conditions to prevent unintended state retention.
Expected behavior:
| Enable | A1 | A0 | Match | |----------|------|------|---------| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 |
The synthesis log flags an unintended latch on the Match output. Simulation shows Match = 1 for input Enable=0, A1=1, A0=1 when following a cycle where Match was previously asserted. The output fails to return to 0 when Enable is deasserted. Inspect the circuit and correct the fault.
Constraints
- Only pure combinational logic gates may be used in the final circuit
- Do not use memory elements like D-flip-flops or SR latches to hold state
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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