The Reconvergent Glitch
Static hazards in combinational logic can trigger false clock edges if fed directly into asynchronous resets or sequential logic. The circuit provided implements the Boolean function Y = AB + B'C using a standard AND-OR topology. Every logic gate in this path introduces a finite, non-zero propagation delay.
The inputs are initially stable at A=1, B=1, C=1 before input B transitions from 1 to 0. Evaluate the timing of the internal nodes during this transition. Determine the transient behavior at output Y and identify the architectural conditions required to eliminate this hazard.
Constraints
- Assume all logic gates (AND, OR, NOT) have equal propagation delay
td. - Wire delays are strictly negligible.
- Inputs
AandCremain perfectly stable during the transition ofB.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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