Divide by Three with 50 Percent Duty Cycle
High-speed communication interfaces and PLL feedback loops require precise clock scaling without introducing asymmetric phase distortion. Dividing a clock by an odd integer while maintaining a symmetric high and low time demands sub-cycle phase manipulation.
Construct a clock divider that receives an input clock clk and an active-high synchronous reset rst. The output clk_out must toggle at exactly one-third the frequency of clk with a 50 percent duty cycle.
To ensure consistent test behavior, the phase relationship is strictly defined. After rst is deasserted, the first rising edge of clk must drive clk_out high. The output must then remain high for exactly 1.5 clock cycles before transitioning low for 1.5 clock cycles.
| rst | clk | clk_out | Phase Sequence | |-------|-------|-----------|----------------| | 1 | 0 | 0 | Reset | | 1 | 1 | 0 | Reset | | 0 | 0 | 0 | Deassert Reset | | 0 | 1 | 1 | Rising 1 | | 0 | 0 | 1 | Falling 1 | | 0 | 1 | 1 | Rising 2 | | 0 | 0 | 0 | Falling 2 | | 0 | 1 | 0 | Rising 3 | | 0 | 0 | 0 | Falling 3 |
Constraints
- Use only standard logic gates and D flip-flops.
- Derive the 50 percent duty cycle output by logically combining signals from both positive-edge and negative-edge triggered paths.
- Do not use delay elements, buffers, or asynchronous logic to manipulate the duty cycle.
Topics
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