Programmable Divider Selector
Dynamic frequency scaling relies on adjusting clock speeds on the fly to balance performance and power consumption. A programmable clock divider routes a source clock through a cascade of flip-flops and selects the desired tapped frequency.
The circuit receives a source clock clk_in and a 2-bit control signal sel. It must output a divided clock clk_out according to the selected ratio.
| sel | clk_out | |-------|-----------| | 00 | clk_in / 2 | | 01 | clk_in / 4 | | 10 | clk_in / 8 | | 11 | 0 |
Constraints
- Use D flip-flops to create the divider stages.
- Construct a ripple divider by connecting the inverted output of each stage to the clock input of the subsequent stage.
- Do not create combinational logic loops.
- Clock glitching during selection transitions is acceptable for this design.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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