Glitch Analysis in Combinational Divider Decoding
A combinational decoder evaluates OUT = Q1 AND Q0 to generate a trigger pulse, but unequal routing delays cause Q1 to transition one time step before Q0. Four signals are shown: CLK (clock, period 4), Q1 (early counter MSB), Q0 (delayed counter LSB) and OUT (decoder output, initially 0). Trace OUT across all 16 time steps to identify any transient glitches caused by the misaligned inputs.
Constraints
- Evaluate the logical AND of the inputs strictly at each individual time step.
- A glitch occurs if all inputs to the AND gate are simultaneously high during a transition window.
Topics
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