Clock Phase Shifter 90 Degrees
Double data rate memory interfaces and radio frequency modulation systems rely on quadrature clocks to sample data accurately. Generating two clocks exactly 90 degrees out of phase ensures stable setup and hold margins across high-speed links.
Implement a divide-by-4 clock generator that produces two outputs: clk_0 and clk_90. The clk_90 signal must lag clk_0 by exactly one input clock cycle, which corresponds to 90 degrees of the divided clock period. When rst is asserted high, both outputs must immediately reset to 0. On subsequent clock cycles with rst low, the outputs must follow the quadrature sequence.
| rst | Cycle | clk_0 | clk_90 | |-------|-------|---------|----------| | 1 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | | 0 | 2 | 1 | 1 | | 0 | 3 | 0 | 1 | | 0 | 4 | 0 | 0 | | 0 | 5 | 1 | 0 |
Constraints
- Use only D flip-flops and basic logic gates.
- The outputs must operate at exactly one-fourth the frequency of the base clock.
- Do not use delay elements or buffers to artificially shift the clock phase.
Topics
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