Clock Phase Shifter 180 Degrees
A logical inverter immediately negates its input, while a negative-edge-triggered D flip-flop captures its input only on the HIGH-to-LOW transition of the clock.
Four signals are shown: CLK (clock, period 2), D (data input), CLK_INV (combinational output), and Q_NEG (sequential output, initially 0).
Trace CLK_INV and Q_NEG across all 10 time steps.
Constraints
CLK_INVmust be evaluated combinationally at every time step based directly onCLK.Q_NEGonly updates its internal state whenCLKtransitions from 1 to 0.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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