Clock Doubler Using Gate Delay
Custom ASIC designers sometimes need to multiply clock frequencies locally without the overhead of an analog phase-locked loop. A delay-line clock doubler achieves this by generating a short pulse on every transition of the source clock.
The circuit receives a base clock clk_in and outputs a doubled clock clk_out. The output must pulse high for a brief duration whenever clk_in transitions from 0 to 1 or from 1 to 0. This behavior is achieved by comparing the input clock against a delayed version of itself.
| clk_in | delayed_clk | clk_out | |----------|---------------|-----------| | 0 | 0 | 0 | | 1 | 0 | 1 | | 1 | 1 | 0 | | 0 | 1 | 1 |
Constraints
- Use exactly one XOR gate to drive
clk_out. - Create the delay line using a chain of buffer gates connected in series.
- Do not use any sequential elements like flip-flops or latches.
- The steady-state output of
clk_outmust always resolve to 0.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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