Divide by 5 with 20 Percent Duty Cycle
Generating slower timing references from a high-frequency system clock is a standard requirement for peripheral interfaces. A divide-by-5 circuit steps down the clock frequency while maintaining a predictable pulse width for downstream logic.
The circuit must divide the input clock by 5, producing an output clk_out with a 20% duty cycle. The output clk_out must be high for exactly one clock period and low for four clock periods. The circuit must include an asynchronous, active-low reset rst_n. If the internal state machine powers up in or enters an invalid state, it must recover to a valid counting sequence within one clock cycle.
| rst_n | Internal State | Next State | clk_out | |---------|----------------|------------|-----------| | 0 | X | 0 | 0 | | 1 | 0 | 1 | 1 | | 1 | 1 | 2 | 0 | | 1 | 2 | 3 | 0 | | 1 | 3 | 4 | 0 | | 1 | 4 | 0 | 0 | | 1 | >4 | 0 | 0 |
Constraints
- Implement a 3-bit internal counter to track the current state.
- Force any invalid state (values greater than 4) to transition to state 0 on the next clock edge.
- Drive the output
clk_outhigh only when the internal state is 0. - Use an asynchronous active-low reset
rst_nto initialize the circuit.
Topics
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