Divide by 3 with 50 Percent Duty Cycle
Clock generation networks often require dividing a high-speed reference clock down to lower frequencies for peripheral buses. Achieving a perfect square wave with an odd division factor requires sub-cycle resolution to ensure timing margins remain symmetric.
The circuit takes a continuous input clock clk and an active-high asynchronous reset rst. It must produce an output clock clk_out whose frequency is exactly one-third of the input clk. The output clk_out must maintain exactly a 50 percent duty cycle: it must remain high for 1.5 input clock cycles and low for 1.5 input clock cycles.
| rst | clk Edge | clk_out | |-------|------------|-----------| | 1 | X | 0 | | 0 | Rising 1 | 0 | | 0 | Falling 1 | 0 | | 0 | Rising 2 | 1 | | 0 | Falling 2 | 1 | | 0 | Rising 3 | 1 | | 0 | Falling 3 | 0 |
Constraints
- Use only standard D flip-flops and combinational logic gates.
- Do not use delay elements or phase-locked loops.
- Drive the
clk_outoutput using pure combinational logic based on the internal flip-flop states. - The reset signal
rstmust asynchronously initialize the divider state to zero.
Topics
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