The Unsafe Ring Counter
Shift register based counters are notoriously fragile to single event upsets. A self-correcting 4-bit ring counter uses feedback logic to flush extra ones out of the ring and maintain a valid one-hot state sequence.
Expected behavior:
The combinational feedback circuit computes the next input D0 based on the current state Q0, Q1, Q2, and Q3. To guarantee the counter cycles through the states 1000, 0100, 0010, and 0001 while also recovering from invalid states, D0 must be 1 if and only if Q0, Q1, and Q2 are all 0.
| Q0 | Q1 | Q2 | Q3 | D0 | |------|------|------|------|------| | 1 | 0 | 0 | 0 | 0 | | 0 | 1 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | 0 | | 0 | 0 | 0 | 1 | 1 | | 0 | 0 | 0 | 0 | 1 | | 1 | 1 | 0 | 0 | 0 |
Simulation shows D0 = 0 for input Q0=0, Q1=0, Q2=0, Q3=1. The counter enters an invalid all-zero state instead of wrapping the bit around. Inspect the circuit and correct the fault.
Constraints
- Do not add sequential elements to this block.
- The circuit must remain purely combinational.
- The fix requires replacing or removing exactly one connection or gate.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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