Shift Register Hold Violation
Hold time violations destroy silicon because they cannot be patched by lowering the clock frequency. The schematic shows two consecutive positive-edge triggered D flip-flops, FF1 and FF2, wired as a shift register. The output Q1 connects directly to the input D2 with zero combinational logic in between. Both flip-flops share a clock net CLK, but a routing buffer introduces a delay of t_skew before reaching FF2. The flip-flops have a clock-to-Q contamination delay of t_ccq, a clock-to-Q propagation delay of t_pcq, a setup time of t_su, and a hold time of t_h. Determine the timing conditions that guarantee data is safely captured at FF2 without corruption.
Constraints
- The combinational logic contamination delay and propagation delay are both exactly 0.
- Clock skew
t_skewis defined as the arrival time atFF2minus the arrival time atFF1. - Setup and hold times are internal to the flip-flop characteristics.
Topics
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