Setup Time Under Skew
Physical clock distribution networks introduce routing delays that cause the clock edge to arrive at different registers at different times.
The circuit consists of two flip-flops, FF1 (launch) and FF2 (capture), separated by a combinational logic block. The clock signal CLK originates near FF2 and routes backward to FF1. The clock routing delay from the source to FF2 is 0.5 ns, while the delay to FF1 is 1.2 ns. FF1 and FF2 share the following characteristics: clock-to-Q delay T_cq = 0.8 ns, setup time T_su = 0.5 ns, and hold time T_h = 0.2 ns. The combinational logic delay T_comb is 2.5 ns.
Calculate the timing margins and determine the maximum safe operating frequency for this data path.
Constraints
- Assume zero clock jitter.
- All delays are worst-case maximums unless specified otherwise.
- Clock skew is defined as the difference in clock arrival time between the capture and launch registers.
Topics
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