The Backwards Synchronizer
A standard two-stage synchronizer safely transfers a single-bit signal from a source clock domain to a destination clock domain. The circuit must resolve metastability before the signal reaches the destination logic.
Expected behavior:
The output Data_out must transition exclusively on the rising edge of the destination clock Clk_dst. The synchronized signal takes two Clk_dst cycles to propagate to the output.
Simulation shows that Data_out transitions on the rising edge of Clk_src. When Clk_src is halted, Data_out fails to update even when Clk_dst continues toggling. Inspect the circuit and correct the fault.
Constraints
- Do not add additional flip-flops or gates to the circuit.
- The final circuit must maintain a standard two-stage synchronization pipeline.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.