Unique Case Parallel Logic
High-speed memory controllers map transaction addresses to specific physical memory banks. When decoding these addresses, standard case statements can cause synthesis tools to infer priority routing if the tool cannot mathematically prove the conditions are mutually exclusive. This priority chain severely degrades timing in the critical path.
The module accepts an 8-bit memory address and asserts one of four bank select signals or an error flag. The address space is divided into distinct regions. The top three bits of the address determine the target region. The synthesis tool must be explicitly instructed to evaluate these regions in parallel without priority using the SystemVerilog unique keyword.
Clock edge and reset behaviour: • Clock edge: posedge clk • Reset type: Asynchronous, active-low (rst_n) • Reset polarity: All bank selects and the error flag default to 0 when rst_n is asserted. • Output timing: All outputs are registered and update on the clock edge immediately following the address input.
Address mapping rules: • Addresses 8'h00 to 8'h3F assert bank0_sel • Addresses 8'h40 to 8'h7F assert bank1_sel • Addresses 8'h80 to 8'hBF assert bank2_sel • Addresses 8'hC0 to 8'hDF assert bank3_sel • Addresses 8'hE0 to 8'hFF assert err_flag
Worked trace: Cycle 1: rst_n=0, addr=8'h00 → bank0_sel=0, bank1_sel=0, bank2_sel=0, bank3_sel=0, err_flag=0 Cycle 2: rst_n=1, addr=8'h1A → bank0_sel=0, bank1_sel=0, bank2_sel=0, bank3_sel=0, err_flag=0 (outputs hold reset value until next clock) Cycle 3: rst_n=1, addr=8'h55 → bank0_sel=1, bank1_sel=0, bank2_sel=0, bank3_sel=0, err_flag=0 Cycle 4: rst_n=1, addr=8'hE2 → bank0_sel=0, bank1_sel=1, bank2_sel=0, bank3_sel=0, err_flag=0 Cycle 5: rst_n=1, addr=8'h00 → bank0_sel=0, bank1_sel=0, bank2_sel=0, bank3_sel=0, err_flag=1
{ "signal": [
{ "name": "clk", "wave": "p......" },
{ "name": "rst_n", "wave": "01....." },
{ "name": "addr", "wave": "x=.=.=." , "data": ["8'h1A", "8'h55", "8'hE2"] },
{ "name": "bank0_sel", "wave": "0.1.0.." },
{ "name": "bank1_sel", "wave": "0...1.0" },
{ "name": "err_flag", "wave": "0.....1" }
], "head": { "text": "Sequential address decoding with registered outputs." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all outputs go to 0 when asserted | | addr | input | 8 | Memory address to decode | | bank0_sel | output | 1 | Asserted for addresses 8'h00 to 8'h3F | | bank1_sel | output | 1 | Asserted for addresses 8'h40 to 8'h7F | | bank2_sel | output | 1 | Asserted for addresses 8'h80 to 8'hBF | | bank3_sel | output | 1 | Asserted for addresses 8'hC0 to 8'hDF | | err_flag | output | 1 | Asserted for addresses 8'hE0 to 8'hFF |
Constraints
- Outputs must be registered on
posedge clk. - Reset must be asynchronous and active-low.
- All outputs must default to
0on reset. - The address decode logic must use the
unique caseconstruct to guarantee parallel multiplexer synthesis. - Only one output may be asserted high at any given time.
Topics
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