Unpacked Struct Compilation Failure
Hardware designs frequently group related signals into structures for cleaner routing across the hierarchy. A data router module registers a 64-bit bus into a structured format on the rising clock edge. The upper 32 bits map to an address field and the lower 32 bits map to a payload field. Both fields are driven continuously to output ports.
The solution module captures bus_in into an internal struct on the positive clock edge. Synchronous active-high reset clears both outputs to 0. When reset is de-asserted, address_out receives bits 63 to 32 of bus_in and payload_out receives bits 31 to 0.
Simulation fails with a compilation error. The compiler reports an illegal assignment when attempting to drive the 64-bit bus_in vector directly into the internal struct variable. Inspect the module and correct the fault.
| Signal | Direction | Width | Description | |----------------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst | input | 1 | Synchronous active-high reset; clears both outputs to 0 | | bus_in | input | 64 | Input bus; upper 32 bits are address, lower 32 bits are payload | | address_out | output | 32 | Registered address field; resets to 0 | | payload_out | output | 32 | Registered payload field; resets to 0 |
Constraints
- Clock is positive-edge triggered.
- Reset is synchronous and active-high.
- Both outputs reset to 0.
- The struct fields must be named
addressandpayload, each 32 bits wide. - The struct must be assigned from
bus_inin a single statement inside thealways_ffblock. - Do not modify the module port list.
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.