Valid Bubble Insertion
Pipelined architectures often encounter situations where data flow must be interrupted. If a downstream execution unit is busy, the entire pipeline must stall to prevent data loss. However, if an upstream unit (like an instruction cache) misses, downstream stages should continue processing their valid data while empty "bubbles" are inserted into the front of the pipeline.
The module implements a three-stage pipeline for an 8-bit data path and a 1-bit valid flag. It receives data_in and valid_in, passing them through three internal pipeline registers before outputting them as data_out and valid_out. Two control signals dictate the stall behaviour: stall_downstream and stall_upstream.
When stall_downstream is asserted, the entire pipeline freezes. All three stages hold their current data and valid bits to prevent overwriting unprocessed data. When stall_downstream is deasserted but stall_upstream is asserted, a bubble is inserted into the pipeline. The first stage receives a valid bit of 0 and data of 8'h00, while the second and third stages continue to shift their contents normally. When neither stall signal is asserted, the pipeline shifts normally, loading data_in and valid_in into the first stage.
All registers are positive-edge triggered on clk. An asynchronous, active-low reset rst_n clears all valid bits and data registers in all three stages to 0. The stall_downstream signal has strict priority over stall_upstream.
Worked Trace: • Cycle 1: rst_n=0 → all stages cleared. data_out=0, valid_out=0 • Cycle 2: rst_n=1, data_in=8'hAA, valid_in=1 → Stage 1 gets 8'hAA (valid). data_out=0, valid_out=0 • Cycle 3: data_in=8'hBB, valid_in=1 → Stage 1 gets 8'hBB, Stage 2 gets 8'hAA. data_out=0, valid_out=0 • Cycle 4: data_in=8'hCC, valid_in=1 → Stage 1 gets 8'hCC, Stage 2 gets 8'hBB, Stage 3 gets 8'hAA. data_out=8'hAA, valid_out=1 • Cycle 5: stall_upstream=1 (Bubble) → Stage 1 gets 8'h00 (invalid), Stage 2 gets 8'hCC, Stage 3 gets 8'hBB. data_out=8'hBB, valid_out=1 • Cycle 6: stall_downstream=1 (Freeze) → All stages hold. data_out=8'hBB, valid_out=1 • Cycle 7: stall_downstream=0, stall_upstream=0, data_in=8'h11, valid_in=1 → Stage 1 gets 8'h11, Stage 2 gets 8'h00 (invalid), Stage 3 gets 8'hCC. data_out=8'hCC, valid_out=1
Port Table:
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears all pipeline stages to 0 | | data_in | input | 8 | Input data to the first pipeline stage | | valid_in | input | 1 | Input valid flag for the first pipeline stage | | stall_upstream | input | 1 | When 1, inserts a bubble (data=0, valid=0) into stage 1; stages 2 and 3 shift normally | | stall_downstream | input | 1 | When 1, freezes all pipeline stages; overrides stall_upstream | | data_out | output | 8 | Data from the third pipeline stage | | valid_out | output | 1 | Valid flag from the third pipeline stage |
Constraints
- The module must trigger on the positive edge of
clkand reset on the negative edge ofrst_n. - On reset, all internal stages and outputs must be cleared to 0.
stall_downstreamhas strict priority overstall_upstream. If both are asserted, the pipeline must freeze.- When a bubble is inserted via
stall_upstream, the first stage data must be forced to 8'h00 and its valid bit to 0. - All outputs must be registered, originating directly from the third pipeline stage.
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