Valid Ready Handshake Protocol Monitor

Data streams in modern hardware rely on valid-ready handshakes to manage backpressure. When a downstream peripheral cannot accept more data, it deasserts its ready signal. The upstream master must hold both its valid flag and the data payload perfectly stable until the transaction completes. Verifying this behavior requires a bus functional model (BFM) that deliberately applies backpressure and monitors the master for protocol violations.

The verification module acts as a slave endpoint on a data bus. It generates a ready signal based on a throttle command from the test environment. Simultaneously, it monitors the valid and data signals from the master. If the master asserts valid while ready is low, a stall condition occurs. During a stall, the master is legally required to keep valid asserted and data unchanged on subsequent clock cycles. If the master drops valid or alters data before the transaction completes, the module flags a persistent protocol error.

• Clock edge: posedge clk
• Reset: Asynchronous, active-low rst_n
• Output values on reset: ready goes to 0, error goes to 0
• ready generation: On every clock edge, ready is updated to the inverted value of the throttle input
• error generation: The module must remember the master's valid, ready, and data signals from the previous cycle. If valid was 1 and ready was 0 on the previous clock edge, the current clock edge must see valid equal to 1 and data equal to the previous data. If either condition is false, error transitions to 1 and stays 1 until reset.

Cycle-by-cycle trace: Cycle 1: rst_n=0, throttle=0 → ready=0, error=0 Cycle 2: rst_n=1, throttle=0, valid=1, data=8'hAA → ready=1, error=0 (ready updates to ~throttle) Cycle 3: throttle=1, valid=1, data=8'hBB → ready=0, error=0 (stall begins because ready=0 and valid=1) Cycle 4: throttle=0, valid=1, data=8'hBB → ready=1, error=0 (master held valid and data stable; error remains 0) Cycle 5: throttle=1, valid=1, data=8'hCC → ready=0, error=0 (new transaction; stall begins again) Cycle 6: throttle=0, valid=0, data=8'hCC → ready=1, error=1 (VIOLATION: master dropped valid during stall) Cycle 7: throttle=0, valid=1, data=8'hDD → ready=1, error=1 (error remains latched high)

{ "signal": [
  { "name": "clk",      "wave": "p......" },
  { "name": "rst_n",    "wave": "01....." },
  { "name": "throttle", "wave": "0010100" },
  { "name": "valid",    "wave": "0111101" },
  { "name": "data",     "wave": "=.=.=.=.=.=.=", "data": ["00", "AA", "BB", "BB", "CC", "CC", "DD"] },
  {},
  { "name": "ready",    "wave": "0101011" },
  { "name": "error",    "wave": "0.....1" }
], "head": { "text": "Master correctly holds data 8'hBB during the first stall, but illegally drops valid during the second stall." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all outputs go to 0 when asserted | | throttle | input | 1 | Test environment command; ready becomes ~throttle on the next clock edge | | valid | input | 1 | Master valid signal | | data | input | 8 | Master data payload | | ready | output | 1 | Slave ready signal; resets to 0 | | error | output | 1 | Protocol violation flag; resets to 0 and latches high on error |

Constraints

• Clock edge must be posedge clk and reset must be asynchronous active-low rst_n
• Outputs ready and error must be registered and exactly 0 on reset
• ready must be strictly driven by registering the inverted value of throttle
• A protocol stall condition evaluates as true when valid is 1 and ready is 0
• Once error is asserted to 1, it must remain 1 regardless of future inputs until rst_n is asserted

Topics

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