Yosys FF Count Verification: Edge Detector

Digital systems frequently need to convert a continuous level-sensitive signal into a single-cycle pulse to trigger state machine transitions or increment counters. For example, a button press might last for millions of clock cycles, but the system only wants to increment a counter exactly once when the button is first pressed.

The module receives a synchronous 1-bit input signal d and generates a single-cycle high pulse on the 1-bit output pulse exactly one clock cycle after the input transitions from low to high. To prevent combinational glitches from propagating to downstream logic, the output must be registered.

Timing and Reset Rules

• Clock edge: posedge clk
• Reset type: Asynchronous, active-low (rst_n)
• Output values on reset: pulse goes to 0, and the internal delayed state must also reset to 0
• Registered output: The pulse output must be driven directly by a flip-flop

Worked Trace

Cycle 1: rst_n=0 → internal_state=0, pulse=0 Cycle 2: rst_n=1, d=0 → internal_state=0, pulse=0 Cycle 3: rst_n=1, d=1 → internal_state=1, pulse=1 Cycle 4: rst_n=1, d=1 → internal_state=1, pulse=0 Cycle 5: rst_n=1, d=0 → internal_state=0, pulse=0 Cycle 6: rst_n=1, d=1 → internal_state=1, pulse=1

Waveform

{ "signal": [
  { "name": "clk",   "wave": "p......" },
  { "name": "rst_n", "wave": "01....." },
  { "name": "d",     "wave": "0.1.01." },
  { "name": "pulse", "wave": "0..10.1" }
], "head": { "text": "Synchronous rising edge detector with registered output." } }

Port Table

| Signal | Direction | Width | Description | |---------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset | | d | input | 1 | Synchronous input signal | | pulse | output | 1 | Registered single-cycle pulse output; resets to 0 |

Constraints

• The module must trigger on the positive edge of clk and use an active-low asynchronous rst_n
• The pulse output must be driven directly by a flip-flop without any trailing combinational logic
• Yosys structural constraint: The synthesized module must infer exactly two flip-flops (one for the delayed input, one for the registered output)

Topics

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