Asymmetric Data Width FIFO

System-on-Chip designs frequently bridge high-performance processors and low-speed peripherals. When a 32-bit CPU writes data to an 8-bit UART transmitter, the intermediate buffer must handle both data storage and width conversion. The Asymmetric Data Width FIFO solves this by accepting 32-bit wide writes and providing 8-bit wide reads, internally managing the serialization and pointer scaling required to keep track of the stored bytes.

This module implements a First-In-First-Out memory with a total capacity of four 32-bit words, which equals sixteen 8-bit words. Data is unpacked in little-endian order. When a 32-bit word is written, its least significant byte is read out first, followed by the progressively more significant bytes.

The read interface is combinational. The r_data output continuously reflects the 8-bit word at the current read pointer. Asserting r_en acknowledges that the current byte has been consumed, causing the read pointer to advance on the next clock edge.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset; clears all pointers and flags | | w_en | input | 1 | Write enable; writes w_data on posedge clk if not full | | w_data| input | 32 | 32-bit data input to be pushed into the FIFO | | r_en | input | 1 | Read enable; advances read pointer on posedge clk if not empty | | r_data| output | 8 | Combinational 8-bit data output at the current read pointer | | full | output | 1 | Asserted high when the FIFO cannot accept another 32-bit write | | empty| output | 1 | Asserted high when the FIFO contains no unread 8-bit words |

Constraints

• The FIFO capacity is exactly sixteen 8-bit words.
• Data must be unpacked in little-endian order; w_data[7:0] is read first, followed by w_data[15:8], w_data[23:16], and w_data[31:24].
• r_data is a combinational output. It must output 8'h00 when the FIFO is empty.
• If full is 1, any asserted w_en must be strictly ignored, even if r_en is simultaneously asserted.
• If empty is 1, any asserted r_en must be strictly ignored, even if w_en is simultaneously asserted.
• Simultaneous read and write operations are permitted provided the FIFO is neither strictly full nor strictly empty.

Topics

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