Almost Full and Almost Empty Flags
Burst protocols like AXI need to know if an asynchronous FIFO will be full several cycles in advance to safely halt the pipeline without dropping data. High-latency systems rely on early warning signals, specifically almost full and almost empty flags, to manage flow control across independent clock domains.
This module calculates the almost_full and almost_empty flags for a dual-clock asynchronous FIFO. It operates across two independent clock domains. In the write domain, it converts the synchronized Gray-coded read pointer back to binary, calculates the current fill level, and asserts almost_full if the fill level is greater than or equal to afull_thresh. In the read domain, it converts the synchronized Gray-coded write pointer back to binary, calculates the available words, and asserts almost_empty if the available words are less than or equal to aempty_thresh.
Both clock domains use active-low asynchronous resets. The almost_full flag is registered on the positive edge of wclk and resets to 0. The almost_empty flag is registered on the positive edge of rclk and resets to 1, because an empty FIFO is inherently almost empty. All pointers are ADDR_WIDTH + 1 bits wide to distinguish between completely full and completely empty states.
| Signal | Direction | Width | Description | |---|---|---|---| | wclk | input | 1 | Write domain positive-edge triggered clock | | wrst_n | input | 1 | Write domain asynchronous active-low reset | | wptr_bin | input | ADDR_WIDTH+1 | Write pointer in binary | | sync_rptr_gray | input | ADDR_WIDTH+1 | Read pointer synchronized to write domain in Gray code | | afull_thresh | input | ADDR_WIDTH+1 | Threshold for almost full flag | | almost_full | output | 1 | Registered almost full flag; resets to 0 | | rclk | input | 1 | Read domain positive-edge triggered clock | | rrst_n | input | 1 | Read domain asynchronous active-low reset | | rptr_bin | input | ADDR_WIDTH+1 | Read pointer in binary | | sync_wptr_gray | input | ADDR_WIDTH+1 | Write pointer synchronized to read domain in Gray code | | aempty_thresh | input | ADDR_WIDTH+1 | Threshold for almost empty flag | | almost_empty | output | 1 | Registered almost empty flag; resets to 1 |
*Parameter:* ADDR_WIDTH (default 4)
Constraints
- Clock edges are positive (
wclk,rclk). - Resets are asynchronous and active-low (
wrst_n,rrst_n). - The
almost_fulloutput must be registered onwclkand reset to 0. - The
almost_emptyoutput must be registered onrclkand reset to 1. - Pointer subtraction must utilize the full
ADDR_WIDTH + 1bits to correctly handle pointer wrap-around. - The
almost_fullflag asserts when the calculated fill level is greater than or equal toafull_thresh. - The
almost_emptyflag asserts when the calculated available words is less than or equal toaempty_thresh.
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