Debug Sequential: Incorrect Next State Logic Loop
A finite state machine next-state logic block controls transitions between the IDLE (0) and ACTIVE (1) states based on the Start and Error inputs. The system must return to IDLE immediately whenever Error asserts.
Expected behavior:
| State | Start | Error | Next_State | |---------|---------|---------|--------------| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 0 |
Simulation shows Next_State = 1 for input State=1, Start=0, Error=1. The machine fails to exit the ACTIVE state when an error occurs. Inspect the circuit and correct the fault.
Constraints
- Do not modify the input or output pins.
- Use standard logic gates to resolve the fault.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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