Fault Propagation and Noncontrolling Values
Manufacturing defects in silicon are only detectable if their logical effects can be routed to an observable output pin.
The schematic shows a three-level combinational circuit under test. An internal node N1 is suspected to have a stuck-at-0 (SA0) fault. The propagation path from N1 to the final observable output Y passes sequentially through three logic gates: an OR gate G1, an AND gate G2, and finally an OR gate G3. The off-path inputs to these gates are directly controlled by primary inputs A, B, and C respectively.
Analyze the gate sequence and determine the specific primary input vector required to sensitize the path and propagate the fault at N1 to the output Y.
Constraints
- The circuit contains no reconvergent fanout paths.
- Inputs
A,B, andCare fully controllable primary inputs. - The fault model is a single stuck-at-0 (SA0) at node
N1.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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