Fixed Point Rounding Logic
Digital signal processing pipelines require word length reduction after multiplication operations. Simple truncation introduces a systematic negative bias into the signal, requiring round-to-nearest logic to maintain mathematical accuracy.
The circuit takes an 8-bit input din and produces a 4-bit output dout. The upper four bits din[7:4] represent the integer portion to be kept. The lower four bits din[3:0] represent the fractional portion to be discarded. Implement round-to-half-up logic: conditionally add one to the least significant kept bit based on the value of the most significant discarded bit.
| din | dout | |----------|--------| | 01010000 | 0101 | | 01010111 | 0101 | | 01011000 | 0110 | | 11111000 | 0000 |
Constraints
- Combinational logic only.
- Ignore overflow carry bits beyond the 4-bit output width.
Topics
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