Generate If Optional Pipeline Stage

High-performance IP cores often need to support multiple target frequencies across different silicon technologies. A multiplier might meet timing in a fast technology node with a single pipeline stage, but require an extra stage to meet the clock period in a slower node. Using SystemVerilog generate blocks allows designers to conditionally include or exclude hardware at compile time; this ensures that bypassed stages consume zero registers and zero area in the final synthesized netlist.

The module computes the 32-bit product of two 16-bit unsigned inputs. A parameter controls the pipeline depth. When the parameter is set to 0, the product is registered once and output on the next clock cycle. When the parameter is set to 1, the product is registered, and then that intermediate value is registered a second time before reaching the output, delaying the result by two clock cycles.

• Clock edge: posedge clk
• Reset type: Asynchronous
• Reset polarity: Active-low (rst_n)
• Output values on reset: All pipeline registers and the output p must be cleared to 0.
• Parameter: EXTRA_PIPE dictates the pipeline depth; defaults to 0.

Cycle 1: rst_n=0 → p=0 (for both configurations) Cycle 2: rst_n=1, a=2, b=3 → p=0 (previous) Cycle 3: a=4, b=5 → p=6 (EXTRA_PIPE=0), p=0 (EXTRA_PIPE=1) Cycle 4: a=1, b=1 → p=20 (EXTRA_PIPE=0), p=6 (EXTRA_PIPE=1) Cycle 5: a=0, b=0 → p=1 (EXTRA_PIPE=0), p=20 (EXTRA_PIPE=1)

{ "signal": [
  { "name": "clk",   "wave": "p......" },
  { "name": "rst_n", "wave": "01....." },
  { "name": "a",     "wave": "x====x.", "data": ["2", "4", "1", "0"] },
  { "name": "b",     "wave": "x====x.", "data": ["3", "5", "1", "0"] },
  {},
  { "name": "p",     "wave": "=======", "data": ["0", "0", "0", "6", "20", "1", "0"] }
], "head": { "text": "Pipeline behavior when EXTRA_PIPE is 1." } }

| Parameter | Default | Type | Description | |-----------|---------|------|-------------| | EXTRA_PIPE | 0 | integer | When 1, adds an additional pipeline stage to the output. |

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears all registers to 0 | | a | input | 16 | First multiplicand | | b | input | 16 | Second multiplicand | | p | output | 32 | Product output; delayed by 1 cycle if EXTRA_PIPE=0, or 2 cycles if EXTRA_PIPE=1 |

Constraints

• Must use generate and if constructs to conditionally instantiate the second pipeline stage.
• EXTRA_PIPE must default to 0.
• The multiplier must be purely combinational before the first register; the first register holds the product.
• When EXTRA_PIPE is 0, the intermediate product register drives the output p directly.
• When EXTRA_PIPE is 1, a second register delays the intermediate product by one additional clock cycle.
• rst_n must asynchronously clear all instantiated registers to 0.

Topics

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