Glitch Filtering on Asynchronous Inputs
Mechanical switches and external asynchronous signals often suffer from physical bounce or transient noise. Before these signals can be safely used in a synchronous digital system, they must not only be synchronized to avoid metastability, but also digitally filtered to reject high-frequency glitches.
The module acts as a digital low-pass filter. It samples the incoming signal on every clock cycle. The output updates to a new logic level only when the input has remained perfectly stable at that new level for four consecutive clock cycles. If the input fluctuates before reaching four stable cycles, the output holds its current state.
Timing and Reset Rules: • Clock edge: posedge clk • Reset type: Asynchronous, active-low (rst_n) • On reset, both the internal sampling history and the sync_out register are cleared to 0. • When the internal 4-bit history contains all 1s, sync_out updates to 1. • When the internal 4-bit history contains all 0s, sync_out updates to 0. • For any mixed history (e.g., 1011 or 0100), sync_out holds its previous value.
Worked Trace: Cycle 1: rst_n=0, async_in=0 → history=0000, sync_out=0 Cycle 2: rst_n=1, async_in=1 → history=0001, sync_out=0 Cycle 3: async_in=1 → history=0011, sync_out=0 Cycle 4: async_in=0 → history=0110, sync_out=0 (glitch rejected) Cycle 5: async_in=1 → history=1101, sync_out=0 Cycle 6: async_in=1 → history=1011, sync_out=0 Cycle 7: async_in=1 → history=0111, sync_out=0 Cycle 8: async_in=1 → history=1111, sync_out=1 (stable for 4 cycles)
{ "signal": [
{ "name": "clk", "wave": "p......." },
{ "name": "rst_n", "wave": "01......" },
{ "name": "async_in", "wave": "01.01..." },
{},
{ "name": "history", "wave": "=.======", "data": ["0000","0001","0011","0110","1101","1011","0111","1111"] },
{ "name": "sync_out", "wave": "0......1" }
], "head": { "text": "Input must be stable for 4 cycles to update sync_out" } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset | | async_in | input | 1 | Noisy asynchronous input signal | | sync_out | output | 1 | Debounced and synchronized output |
Constraints
- The
sync_outsignal must be a registered output driven by a flip-flop, not a combinational wire. - You must use a 4-bit shift register to track the history of
async_in. - The output must not update until the shift register contains exactly four identical bits.
- On reset, the output and all internal shift register bits must clear to
0.
Topics
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