Glitch Free Gray Code FSM

Asynchronous clock domains often monitor the state of an FSM residing in a different domain. If the FSM state is standard binary encoded, multiple bits transitioning simultaneously (e.g., from 3'b011 to 3'b100) can cause the receiving domain to sample intermediate garbage states like 3'b111 or 3'b000. To prevent this, the FSM state must be Gray coded, ensuring a Hamming distance of exactly 1 between any two connected states.

A memory controller FSM outputs its current state directly on state_out. The FSM has 6 states mapped to specific 3-bit encodings.

• IDLE (3'b000): Waits for req. If req=1, transitions to ACTIVE.
• ACTIVE (3'b001): Samples rw (Read/Write). If rw=1, transitions to READ. If rw=0, transitions to WRITE.
• READ (3'b011): Waits for ack. If ack=1, transitions to END_R.
• WRITE (3'b101): Waits for ack. If ack=1, transitions to END_W.
• END_R (3'b010): Automatically transitions back to IDLE on the next clock edge.
• END_W (3'b100): Automatically transitions back to IDLE on the next clock edge.

The FSM operates on the positive edge of clk. An asynchronous active-low reset rst_n forces the FSM into the IDLE state. The ACTIVE, END_R, and END_W states do not wait for any external acknowledgment to leave their states; they evaluate their next state unconditionally or based purely on rw on the very next clock edge.

| Signal | Direction | Width | Description | |-------------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; resets state to 3'b000 | | req | input | 1 | Request signal; initiates sequence from IDLE | | rw | input | 1 | Read/Write select (1=Read, 0=Write); sampled only in ACTIVE | | ack | input | 1 | Acknowledge signal; advances READ or WRITE states | | state_out | output | 3 | Current FSM state; updated synchronously on clk |

Constraints

• The FSM must update its state synchronously on the positive edge of clk.
• Reset must be asynchronous, active-low, and force state_out to 3'b000.
• State encodings must exactly match the 3-bit values defined in the specification.
• rw must only dictate the branch direction when sampled during the ACTIVE state.
• req and ack must be ignored in states where they are not explicitly evaluated.

Topics

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