One Hot Encoding Flip Flop Count

MediumVerilog / SystemVerilogBuild

High frequency digital systems often encounter critical path bottlenecks in the next state logic of complex state machines. One hot encoding solves this by assigning a dedicated flip flop to every state. This increases the total register count but drastically reduces combinational logic depth, allowing the circuit to run at a higher clock frequency.

The solution module acts as a 7-stage sequence controller. It transitions through seven distinct states (S0 through S6). S0 is the idle state. When start is asserted, it moves to S1. From S1 to S5, it advances to the next sequential state only when step is asserted. From S6, it unconditionally returns to S0 on the next clock cycle. To ensure one hot encoding is used, the module outputs its internal state directly as a 7-bit vector state_out, where bit 0 represents S0, bit 1 represents S1, and so on up to bit 6 for S6. A combinational done flag is also provided, which is asserted strictly when the FSM is in S6.

The circuit is synchronized to the positive edge of clk and uses an asynchronous active-low reset rst_n. On reset, the FSM enters S0, making the output 7'b0000001.

Cycle 1: rst_n=0, start=0, step=0 -> state_out=7'b0000001, done=0 (Reset to S0) Cycle 2: rst_n=1, start=1, step=0 -> state_out=7'b0000010, done=0 (Transition to S1) Cycle 3: rst_n=1, start=0, step=0 -> state_out=7'b0000010, done=0 (Hold in S1) Cycle 4: rst_n=1, start=0, step=1 -> state_out=7'b0000100, done=0 (Transition to S2) Cycle 5: rst_n=1, start=0, step=1 -> state_out=7'b0001000, done=0 (Transition to S3) Cycle 6: rst_n=1, start=0, step=1 -> state_out=7'b0010000, done=0 (Transition to S4) Cycle 7: rst_n=1, start=0, step=1 -> state_out=7'b0100000, done=0 (Transition to S5) Cycle 8: rst_n=1, start=0, step=1 -> state_out=7'b1000000, done=1 (Transition to S6)

flowchart LR
    RESET(( )) -->|reset| S0
    S0((S0)) -->|start=1| S1
    S0 -->|start=0| S0
    S1((S1)) -->|step=1| S2
    S1 -->|step=0| S1
    S2((S2)) -->|step=1| S3
    S2 -->|step=0| S2
    S3((S3)) -->|step=1| S4
    S3 -->|step=0| S3
    S4((S4)) -->|step=1| S5
    S4 -->|step=0| S4
    S5((S5)) -->|step=1| S6
    S5 -->|step=0| S5
    S6(["S6 ★"]):::out -->|unconditional| S0
    classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff

{ "signal": [
  { "name": "clk",       "wave": "p......." },
  { "name": "rst_n",     "wave": "01......" },
  { "name": "start",     "wave": "010....." },
  { "name": "step",      "wave": "00011111" },
  {},
  { "name": "state_out", "wave": "========", "data": ["7'h01", "7'h02", "7'h02", "7'h04", "7'h08", "7'h10", "7'h20", "7'h40"] },
  { "name": "done",      "wave": "0......1" }
], "head": { "text": "Progression from S0 through S6." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; sets state_out to 7'b0000001 | | start | input | 1 | Triggers transition from S0 to S1 | | step | input | 1 | Triggers transitions from S1 through S5 | | state_out | output | 7 | Current one-hot state vector | | done | output | 1 | Combinational output; asserted high strictly when in S6 |

Constraints

clk is positive-edge triggered and rst_n is an asynchronous active-low reset.
On reset, the FSM must enter S0, making state_out exactly 7'b0000001.
state_out must strictly follow one-hot encoding for all seven states.
done must be a combinational output that evaluates to 1 when the FSM is in S6, and 0 otherwise.
start is only observed when the FSM is in S0.
step is only observed when the FSM is in S1, S2, S3, S4, or S5.
The transition from S6 back to S0 is unconditional and occurs on the next clock edge regardless of start or step.

Topics

FSMOptimizationOne-HotSynthesis

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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

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Constraints

clk is positive-edge triggered and rst_n is an asynchronous active-low reset.
On reset, the FSM must enter S0, making state_out exactly 7'b0000001.
state_out must strictly follow one-hot encoding for all seven states.
done must be a combinational output that evaluates to 1 when the FSM is in S6, and 0 otherwise.
start is only observed when the FSM is in S0.
step is only observed when the FSM is in S1, S2, S3, S4, or S5.
The transition from S6 back to S0 is unconditional and occurs on the next clock edge regardless of start or step.

Topics

FSMOptimizationOne-HotSynthesis

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

One Hot Encoding Flip Flop Count

Constraints

Topics

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One Hot Encoding Flip Flop Count

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