Identify a Static Hazard Glitch
A combinational logic circuit implements the function Y = (A AND B) OR (NOT_A AND C) to demonstrate a static-1 hazard.
Four signals are shown: primary inputs A, B, and C, and the internal signal NOT_A (the inverted value of A, delayed by one time step due to gate propagation).
Trace the output signal Y across all 8 time steps to reveal the glitch pulse caused by the mismatched delay.
Constraints
- Evaluate the logic function exactly as written using the current values of the signals at each individual time step.
- The output
Ydepends only on the given states ofA,B,C, andNOT_Aat that exact moment.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.