In Place Absolute Value with Overflow

MediumVerilog / SystemVerilogBuild

Fixed width datapath architectures often perform arithmetic operations where bit growth is impossible due to memory or bus constraints. When calculating the absolute value of a signed integer in place, a critical edge case arises: the most negative number cannot be represented as a positive value within the same bit width.

The module computes the absolute value of an 8-bit signed two's complement input. If the input is negative, it is negated to produce a positive magnitude. Because an 8-bit signed integer ranges from negative 128 to positive 127, the absolute value of negative 128 requires 9 bits. When the input is exactly negative 128, the module must assert an overflow flag and output the truncated 8-bit result (which evaluates to 128 in unsigned binary, or 8'h80).

Timing and reset rules: • Clock edge: posedge clk • Reset type: Asynchronous • Reset polarity: Active-low (rst_n) • Output values on reset: val_out and overflow must both be strictly 0. • All outputs are registered. There is no combinational bypass.

Worked trace: • Cycle 1: rst_n=0 → val_out=8'h00, overflow=0 (Reset applied) • Cycle 2: rst_n=1, val_in=8'h05 (5) → val_out=8'h00, overflow=0 (Outputs held at 0 from reset) • Cycle 3: rst_n=1, val_in=8'hFE (negative 2) → val_out=8'h05, overflow=0 (Absolute value of 5) • Cycle 4: rst_n=1, val_in=8'h80 (negative 128) → val_out=8'h02, overflow=0 (Absolute value of negative 2) • Cycle 5: rst_n=1, val_in=8'h00 (0) → val_out=8'h80, overflow=1 (Overflow flagged for negative 128) • Cycle 6: rst_n=1, val_in=8'h00 (0) → val_out=8'h00, overflow=0 (Absolute value of 0)

{ "signal": [
  { "name": "clk",      "wave": "p......" },
  { "name": "rst_n",    "wave": "01....." },
  { "name": "val_in",   "wave": "x====x.", "data": ["8'h05", "8'hFE", "8'h80", "8'h00"] },
  { "name": "val_out",  "wave": "======.", "data": ["8'h00", "8'h00", "8'h05", "8'h02", "8'h80", "8'h00"] },
  { "name": "overflow", "wave": "0...10." }
], "head": { "text": "Pipeline trace showing normal absolute value and the negative 128 overflow edge case." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; drives all outputs to 0 | | val_in | input | 8 | Signed two's complement input value | | val_out | output | 8 | Absolute value of the input, registered | | overflow | output | 1 | Asserted high when val_in is exactly negative 128, registered |

Constraints

Clock edge and reset polarity: posedge clk, active-low asynchronous rst_n.
Output values on reset: Both val_out and overflow must evaluate to exactly 0.
Bit widths and valid ranges: Input and output are 8-bit. Input is treated as signed two's complement.
Wrap, saturation or overflow behaviour: When input is negative 128 (8'h80), val_out must be 8'h80 and overflow must be 1.
Registered outputs: All outputs must be updated only on the positive edge of clk or asynchronous reset.

Topics

Twos ComplementALUDatapathEdge Cases

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Constraints

Clock edge and reset polarity: posedge clk, active-low asynchronous rst_n.
Output values on reset: Both val_out and overflow must evaluate to exactly 0.
Bit widths and valid ranges: Input and output are 8-bit. Input is treated as signed two's complement.
Wrap, saturation or overflow behaviour: When input is negative 128 (8'h80), val_out must be 8'h80 and overflow must be 1.
Registered outputs: All outputs must be updated only on the positive edge of clk or asynchronous reset.

Topics

Twos ComplementALUDatapathEdge Cases

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

In Place Absolute Value with Overflow

Constraints

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In Place Absolute Value with Overflow

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