Localparam Derivation with Clog2

Reusable memory structures like FIFOs are instantiated hundreds of times across a large System-on-Chip. Requiring the instantiating engineer to manually pass both the memory depth and the corresponding address pointer width as separate parameters invites dangerous mismatch bugs. A robust module derives its internal sizing automatically from the minimum required parameters.

This module is a synchronous FIFO that derives its internal pointer sizes automatically. It accepts DATA_WIDTH and DEPTH as parameters. Internally, it must use the SystemVerilog $clog2 function to calculate a localparam for the address width. The FIFO supports standard write and read operations, maintaining full and empty flags.

Positive-edge triggered clock clk. Asynchronous active-low reset rst_n. On reset, all internal pointers, counters, and the read_data output must be driven to 0. The empty flag must be 1, and the full flag must be 0.

Priority and edge cases: • If write_en is asserted and the FIFO is not full, write_data is written and the internal write pointer increments. • If read_en is asserted and the FIFO is not empty, data is read into read_data and the internal read pointer increments. • If both write_en and read_en are asserted: • If the FIFO is neither full nor empty, both operations execute simultaneously. • If the FIFO is full, the read executes and the write is ignored. • If the FIFO is empty, the write executes and the read is ignored. • Writes to a full FIFO (without a simultaneous read) are ignored. • Reads from an empty FIFO (without a simultaneous write) are ignored, and read_data holds its previous value.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset | | write_en | input | 1 | Write enable | | write_data | input | DATA_WIDTH | Data to be written | | read_en | input | 1 | Read enable | | read_data | output | DATA_WIDTH | Registered read data | | full | output | 1 | Asserted when the FIFO cannot accept more writes | | empty | output | 1 | Asserted when the FIFO has no data to read |

Constraints

• You must declare a localparam for the address width using $clog2(DEPTH).
• DEPTH will always be a power of 2 (e.g., 4, 8, 16, 32).
• read_data, full, and empty must update on the positive edge of clk (or immediately on rst_n assertion).
• You must not use any external modules or macros.

Topics

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