Mixed Array Memory Mapping
High-performance CPU caches rely on set-associative tag arrays to determine if a specific memory address is currently cached. A 4-way set-associative cache requires checking four distinct tag entries for a given index simultaneously. Managing this data efficiently requires combining packed and unpacked dimensions to model the exact hardware topology of sets and ways.
The module maintains a memory structure for 16 sets, where each set contains 4 ways. Each way holds an 8-bit tag and a 1-bit valid flag. The module supports synchronous writes to update a specific way within a set, and combinational reads to instantly extract the tag and valid bit for a requested index and way.
Timing and reset rules are as follows: • Clock edge: clk is positive-edge triggered. • Reset type: rst_n is an asynchronous, active-low reset. • On reset: All 64 valid bits and 64 tags in the entire memory array must be immediately cleared to 0. • Write operation: On the positive edge of clk, if w_en is 1, the w_valid and w_tag inputs are written to the memory location specified by w_index and w_way. • Read operation: Outputs r_valid and r_tag are purely combinational. They continuously output the contents of the memory at r_index and r_way. • Priority rule: If a read and write target the exact same index and way simultaneously, the read will output the old data, as the new data is not committed until the clock edge.
Cycle 1: rst_n=0 → r_valid=0, r_tag=0
Cycle 2: rst_n=1, w_en=1, w_index=5, w_way=1, w_valid=1, w_tag=8'hAA, r_index=5, r_way=1 → r_valid=0, r_tag=0 (memory updates on next edge)
Cycle 3: w_en=0, r_index=5, r_way=1 → r_valid=1, r_tag=8'hAA
Cycle 4: w_en=1, w_index=5, w_way=2, w_valid=1, w_tag=8'hBB, r_index=5, r_way=1 → r_valid=1, r_tag=8'hAA
Cycle 5: w_en=0, r_index=5, r_way=2 → r_valid=1, r_tag=8'hBB{ "signal": [
{ "name": "clk", "wave": "p......" },
{ "name": "rst_n", "wave": "01....." },
{ "name": "w_en", "wave": "01010.." },
{ "name": "w_index", "wave": "x=x=x..", "data": ["5", "5"] },
{ "name": "w_way", "wave": "x=x=x..", "data": ["1", "2"] },
{ "name": "w_valid", "wave": "x1x1x.." },
{ "name": "w_tag", "wave": "x=x=x..", "data": ["AA", "BB"] },
{ "name": "r_index", "wave": "======= ", "data": ["0", "5", "5", "5", "5", "5", "5"] },
{ "name": "r_way", "wave": "======= ", "data": ["0", "1", "1", "1", "2", "2", "2"] },
{ "name": "r_tag", "wave": "==.=.=.", "data": ["0", "AA", "BB"] },
{ "name": "r_valid", "wave": "0..1..." }
], "head": { "text": "Combinational read instantly reflects written data after the clock edge." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset | | w_en | input | 1 | Write enable | | w_index | input | 4 | Set index for write operation (0 to 15) | | w_way | input | 2 | Way selector for write operation (0 to 3) | | w_valid | input | 1 | Valid bit to be written | | w_tag | input | 8 | Tag data to be written | | r_index | input | 4 | Set index for combinational read | | r_way | input | 2 | Way selector for combinational read | | r_valid | output | 1 | Combinational output of the valid bit at the read address | | r_tag | output | 8 | Combinational output of the tag at the read address |
Constraints
- The design must register writes on the positive edge of
clk. - The outputs
r_validandr_tagmust be purely combinational. - The entire memory structure must be cleared to 0 when
rst_nis asserted. - You must use a single multidimensional array declaration to model the sets and ways.
Topics
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