Modulo-13 Counter Monitor

Automated verification is essential for catching corner-case bugs in sequential logic. Relying on visual waveform inspection for counters often misses illegal state transitions or incorrect wrap-around behavior. A self-checking monitor module continuously observes a DUT (Device Under Test) and flags violations in real-time.

The monitor module evaluates the output of a modulo-13 counter. It observes the counter's enable signal and current count value. It maintains a history of the previous clock cycle's state to predict the expected current count. It asserts an error flag immediately on the clock cycle where a violation is detected.

Clock edge is posedge. Reset is rst_n, which is asynchronous and active-low. On reset, the internal history is cleared to 0 and err outputs 0. The err signal is a registered output updated on every posedge clk.

The err signal is asserted to 1 if any of the following occur: • count exceeds 12. • On the previous cycle en was 1, and the current count did not increment correctly (wrapping from 12 to 0). • On the previous cycle en was 0, and the current count changed from the previous cycle.

If no violation occurs, err is 0. It evaluates cycle-by-cycle and does not latch indefinitely.

Cycle 1: rst_n=0, en=0, count=0 → err=0 (Reset) Cycle 2: rst_n=1, en=1, count=0 → err=0 (prev_en=0, expected 0, got 0) Cycle 3: rst_n=1, en=1, count=1 → err=0 (prev_en=1, expected 1, got 1) Cycle 4: rst_n=1, en=0, count=2 → err=0 (prev_en=1, expected 2, got 2) Cycle 5: rst_n=1, en=1, count=3 → err=1 (prev_en=0, expected 2, got 3)

{ "signal": [
  { "name": "clk",   "wave": "p....." },
  { "name": "rst_n", "wave": "01...." },
  { "name": "en",    "wave": "01.01." },
  { "name": "count", "wave": "=.====", "data": ["0", "0", "1", "2", "3"] },
  {},
  { "name": "err",   "wave": "0....1" }
], "head": { "text": "Cycle-by-cycle evaluation of the error flag." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears internal history and err to 0 | | en | input | 1 | Enable signal observed from the DUT | | count | input | 4 | Current count value observed from the DUT | | err | output | 1 | Registered error flag; asserts to 1 if a violation is detected |

Constraints

• err must be a registered output updated on posedge clk.
• rst_n is an asynchronous active-low reset.
• On reset, err must be forced to 0, and the internal history of en and count must be cleared to 0.
• The modulo-13 counter wraps from 12 back to 0. Any count value from 13 to 15 is strictly illegal and must immediately flag an error.
• The monitor evaluates cycle-by-cycle. The err flag must return to 0 on the next clock edge if the subsequent transition is valid. Do not latch the error indefinitely.

Topics

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