Observability Blockers
High-reliability silicon requires every internal node to be both controllable from primary inputs and observable at primary outputs. The datapath shown contains an 8-bit adder whose sum output SUM[7:0] feeds into a 2-to-1 multiplexer. The multiplexer select line SEL chooses between the adder's sum when SEL = 1 and a bypass data bus DATA[7:0] when SEL = 0. During standard operation, SEL is held at 0 for 99 percent of clock cycles. The adder's carry-out bit C_OUT is routed through an AND gate with a control signal EN_CARRY before reaching the primary output Z. Determine the exact conditions required to make a fault at C_OUT observable at Z and evaluate the masking effect of the multiplexer on the adder's internal nodes.
Constraints
SELandEN_CARRYare independent single-bit control signals.- The fault model assumes a single stuck-at fault.
DATA[7:0]is fully controllable from primary inputs.
Topics
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