Packed Array Endianness Extraction

Network interfaces and memory controllers frequently bridge systems operating with different byte-order conventions. When a 64-bit AXI bus carrying Little-Endian data interfaces with a Big-Endian packet processor, the hardware must swap the byte order on the fly to prevent data corruption. SystemVerilog packed arrays provide a structural way to map and slice these contiguous bit vectors without relying on error-prone mathematical bit indexing.

The module receives a continuous 64-bit data stream. When the input is valid, the circuit extracts the eight individual bytes from the 64-bit word, completely reverses their order, and registers the result to the output. Byte 0 (bits 7:0) moves to Byte 7 (bits 63:56), Byte 1 moves to Byte 6, and so forth. When the input is not valid, the output maintains its previous state.

Timing and reset rules: • Clock edge: posedge clk • Reset type: Asynchronous, active-low (rst_n) • Output values on reset: data_out must be driven to 64'h0000000000000000. • Priority rules: Reset has the highest priority. When reset is de-asserted, valid_in controls whether new data is captured or the old data is held. • Registered output: data_out updates one clock cycle after valid_in is asserted.

Worked Trace: • Cycle 1: rst_n=0, valid_in=0, data_in=64'hx → data_out=64'h0000000000000000 • Cycle 2: rst_n=1, valid_in=1, data_in=64'hAABBCCDDEEFF1122 → data_out=64'h0000000000000000 (capturing) • Cycle 3: rst_n=1, valid_in=0, data_in=64'hx → data_out=64'h2211FFEEDDCCBBAA (holding) • Cycle 4: rst_n=1, valid_in=1, data_in=64'h0102030405060708 → data_out=64'h2211FFEEDDCCBBAA (capturing) • Cycle 5: rst_n=1, valid_in=0, data_in=64'hx → data_out=64'h0807060504030201 (holding) • Cycle 6: rst_n=1, valid_in=0, data_in=64'hx → data_out=64'h0807060504030201 (holding)

{ "signal": [
  { "name": "clk", "wave": "p....." },
  { "name": "rst_n", "wave": "01...." },
  { "name": "valid_in", "wave": "01010." },
  { "name": "data_in", "wave": "x=x=x.", "data": ["64'hAABB..22", "64'h0102..08"] },
  { "name": "data_out", "wave": "=.=.=.", "data": ["0", "64'h2211..AA", "64'h0807..01"] }
], "head": { "text": "Byte reversal with valid signal registering." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; drives data_out to 0 when asserted | | valid_in | input | 1 | Active-high enable; when 1, input data is captured and reversed | | data_in | input | 64 | Incoming 64-bit data word | | data_out | output | 64 | Registered 64-bit data word with reversed byte order |

Constraints

• Use posedge clk and asynchronous active-low rst_n.
• On reset, data_out must be exactly 64'h0000000000000000.
• When valid_in is 0, data_out must hold its previous value.
• Do not use manual mathematical bit slicing (e.g., data_in[63:56]). You must use a SystemVerilog packed array cast or declaration to access the bytes.

Topics

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